This is the second part in a series of introductory articles on SystemVerilog (SV) object oriented programming (OOP). In the first article, we covered the basics of the class data type and the history ...

SystemVerilog supports templates for generic code writing using parameterized classes. Here we’re going to describe some of the design patterns in the code that make up the UVM base class library.

This part of the handbook explores the use of SystemVerilog for verification and then look at the benefits and drawbacks of using SystemVerilog. In the next chapter we take a brief tour of the ...