Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

SALT LAKE CITY — Sun Microsystems vice president Ivan Sutherland laid out an integrated path to asynchronous chip design at the Async 2001 conference held Mar. 11-14 , proposing that developers look ...

In the simulation and verification world, particularly with regard to system-on-a-chip (SoC) design closure, certain fault types have made their way to silicon with greater frequency. Many of today's ...

As design sizes continue to grow, proliferation of internal and external protocols, along with aggressive power requirements are driving an explosion in the number of asynchronous clocks in today’s ...

Asynchronous, or clockless, logic–an alternative to standard digital circuits that avoids many of their problems–is beginning to look attractive for embedded designs in consumer electronics and mobile ...