Field-programmable gate arrays (FPGAs) are becoming an increasingly popular tool for applications where high performance, low latency and power efficiency are requires. Since an FPGA can be ...
Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...
The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. (March 2018: Link dead. Try the Wayback Machine.) Programmable logic devices are ...
SAN JOSE, Calif. – Pc-board tool vendor Altium Ltd. (Sydney, Australia) will expand its horizons with the launch this week of an ambitious tool environment that aims to help pc-board designers expand ...
We’re really not supposed to start a feature like this; but this hack is awesome. It’s a game of Snake implemented by an FPGA dev board. It uses a 16×16 LED matrix as the display and an SNES ...
I just received an email from a reader asking a rather interesting question. His message read as follows: Greetings Mr Maxfield. I have been enjoying your PLDL Newsletter. The personal touches of your ...
Fifteen years ago verification of FPGA designs was easy but as the size of FPGAs has increased so have the verification challenges, Jerry Kaczynski explains. Today it is not unusual for FPGA users to ...
FREIBURG, GERMANY and ALAMEDA, CA--(Marketwired - May 1, 2014) - Electronic Design Automation (EDA) component software leaders Concept Engineering and Verific Design Automation today announced ...
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